An example of one type of conventional high voltage lateral MISFETs with low on-resistance characteristics is shown in FIG. 1. A high resistive n.sup.- extended drain 10 is formed in a p.sup.- substrate 8 between a p base region 12 and an n.sup.+ drain region 14 to reduce an electric field between a source region 16 and the drain region 14. A gate oxide layer 18 under a gate electrode 20 is thicker at the drain side in order to reduce electric field in the n.sup.- extended drain 10. Generally, lateral MISFETs consist of the following four regions shown in FIG. 1: (1) a source region with a distance of 1.sub.1, (2) a channel region with a distance of 1.sub.2, (3) an extended drain region with a distance of 1.sub.3, and (4) a drain region with a distance of 1.sub.4. The pitch of the device is the sum of 1.sub.1 +1.sub.2,+1.sub.3 +1.sub.4 and determines the packing density of the device and its specific on-resistance. The smaller the pitch, the higher the packing density and the lower the on-resistance per unit am& Present state of the art MISFETs with a breakdown voltage of 80 V require 13 to be 3 gm to reduce the electric field near the drain and prevent premature breakdown. The remaining parameters (1.sub.1, 1.sub.2, and 1.sub.4) do not influence the breakdown voltage significantly and are required to be 1.5 .mu.m, 2 .mu.m, and 1.5 .mu.m respectively for 1.sub.1, 1.sub.2 and 1.sub.4 (for a 1 .mu.m design rule). Thus, the distance or length of the n.sup.- extended drain 10 is the largest among all of the regions and must be increased as the breakdown voltage of the MISFET increases. As a result, the packing density of the MISFET is sacrificed and on-resistance increases. MISFETS with the above-described structure have already been described. See, for example, T. Efland, et al., "Self-Aligned RESURF To LOCOS Region LDMOS Characterization shows Excellent Rsp vs BV Performance" Proceedings ISPSD'96, pp. 147-150, 1996, the contents of which are incorporated herein by reference.
Results of on-state simulations performed for the structure shown in FIG. 1 with a substrate doping level of 7.times.10.sup.14 cm.sup.3, an n.sup.- extended drain surface doping concentration of 7.times.10.sup.17 cm.sup.3 and a junction depth of 1.4 .mu.m are illustrated in FIG. 2. For such simulations, the specific on-resistance of the device is estimated to be 1.6 m.OMEGA.-cm.sup.2 for a breakdown voltage of 80 V.
To overcome the packing density limitation discussed above, MISFETs using trench structures have been proposed by N. Fujishima, et al. in U.S. patent application Ser. No. 08/547,910. As illustrated in FIG. 3, a channel 24 and an n.sup.- extended drain 26 are located vertically at a side-wall of a trench formed in a substrate 28. Since the trench MISFET has the n.sup.- extended drain 26 between a source region 31 and a drain region 32, and a thick gate oxide 34 between a gate electrode 36 and the drain region 32, it is possible to optimize the structure to get almost the same current handling capability in the unit cell as the conventional MISFET without reducing the breakdown voltage. The pitch in this case is determined by the sum of 1.sub.1, 1.sub.6, and 1.sub.5, which typically have values of 1.5 .mu.m, 2.0 .mu.m and 0.5 .mu.m respectively (for minimum 1 .mu.m design rules) resulting in half the pitch of the structure in FIG. 1. Therefore, packing density per unit area of the MISFET can be increased and a reduction in on-resistance per unit area achieved.
However, for the device of FIG. 3, two additional masks are needed to define the silicon trench and the drain contact holes. The resulting process also requires strict alignment tolerance among these three masks. In addition, two deep directional etching steps are needed to define the gate and make the drain contact hole inside the initial silicon trench.
In view of the above, it is an object of the present invention to provide a lateral MISFET incorporating a high packing density trench structure and offering high breakdown voltage with low on-resistance and a method of manufacturing the lateral MISFET.